The present invention pertains to semiconductor logic devices and, more particularly, to a system for storing and retrieving the contents of functional registers in semiconductor logic devices at selected stages of operation without interrupting logic execution.
In connection with the design and development of microprocessors and other semiconductor logic devices it is necessary to debug functional problems that arise during testing of the devices. This testing is a large component of the overall development time for a new logic device, and consumes significant computing and human resources. Current product design cycles and development costs do not permit complete regression analysis at design time due to the large number of possible opcode/function combinations, limited bandwidth of the test case generation and computing and human resource constraints.
As such, testing of logic devices must be performed in a carefully targeted manner using, for example, trace buffers or JTAG (joint test action code) support functionality. To test a logic device using JTAG support, hooks are provided in the logic design that breakpoint or halt an operating function when a breakpoint instruction is received. After breakpointing the operation the JTAG support function reads out data from the requested registers through a JTAG port. Then the application is restarted and runs until the next breakpoint is encountered. Unfortunately, the freezing of a function can break the application undergoing debug. In timing critical or real-time code, e.g., code for controlling a disk drive, such breakage of the application can render the JTAG support function inoperable.
For these and other reasons current techniques for testing and debugging logic devices, particularly pipelined microprocessor designs, are not entirely satisfactory.
One aspect of the present invention is a logic device having a functional execution period with a plurality of execution cycles. The device comprises a plurality of functional registers, each for storing data during an execution cycle and a plurality of shadow registers, each associated with one of the plurality of functional registers and capable of storing a copy of data provided to the associated one of the plurality of functional registers during the functional execution period without interrupting the execution cycles. The device further includes control logic connected to the plurality of shadow registers for controlling when data provided to the plurality of functional registers is stored in the plurality of shadow registers and for retrieving data from the plurality of shadow registers without interrupting the plurality of execution cycles.
Another aspect of the present invention is a logic register combination for use in a logic device having a functional execution period with a plurality of execution cycles. The combination comprises a plurality of functional registers, each for storing data during an execution cycle and a plurality of shadow registers, each associated with one of the plurality of functional registers and capable of storing a copy of data provided to the associated one of the plurality of functional registers during the functional execution period without interrupting the execution cycles.
Still another aspect of the present invention is a method of determining the operational state of a logic device having a plurality of first registers in which data is stored and a plurality of second registers, each second register associated with at least one of said first registers, further wherein the logic device has an execution period with a plurality of execution cycles. The method comprises the step of storing data present in each of the plurality of first registers in an associated one of the plurality of second registers without interrupting execution cycles of the plurality of first registers. Next, data stored in the plurality of second registers is retrieved without interrupting execution cycles of the plurality of first registers. Finally, the data retrieved in the previous step is used to determine the operational state of the logic device.
Yet another aspect of the present invention is a method of debugging a microprocessor having a plurality of L1 registers, a plurality of L2 registers and a plurality of shadow registers, all arranged so that one of the plurality of L1 registers and one of the plurality of L2 registers is associated with each of the plurality of shadow registers, with the plurality of L1 registers, the plurality of L2 registers and plurality of shadow registers being arranged in a pipelined architecture. As the first step of the method, data is provided to the plurality of shadow registers. Next, the data in each of the plurality of shadow registers is provided to a corresponding respective one of the plurality of L2 registers as a function of event type, execution cycle and shadow register address. Finally, a logic operation is performed on the data provided to the L2 registers.